1. Field of the Invention
The present invention relates to a method and apparatus for efficiently designing a circuit design, and more particularly, to a method and apparatus for selecting input, output, and/or bi-directional buffers from a component library, and interconnecting the components automatically in accordance with a set of circuit design assembly rules.
2. Description of the Prior Art
Custom and semi-custom integrated circuit designs, such as Application Specific Integrated Circuits (ASICs), are typically designed by assembling predefined components or macro cells selected from a design library. The use of predefined components is often desirable to expedite the design process because many similar components may be used throughout the circuit design. The components or macro cells are often designed to accommodate a variety of drive strength and control applications. For example, a particular output buffer may be selected from a variety of output macro cells, each having a different drive strength characteristic. This may be desirable because the resistive and/or capacitive load may be different for a selected output pin. Further, some of the I/O may be in critical timing paths, and thus it may be desirable to optimize the output drive of these I/O to maximize the performance of the timing path.
Interconnecting input, output, and bi-directional buffers can be time consuming and tedious, particularly if boundary scan or other test structures are included in the circuit design. For board testing purposes, it is common to provide a boundary scan path that includes each I/O buffer of an integrated circuit. This may allow each of the I/O pads of the integrated circuit to be both controllable and observable, and may help isolate an error to a particular integrated circuit on the board, or to a particular trace on the board.
To provide boundary scan, the I/O buffers typically must have special test logic included therein. The test logic that is required often depends on the type of buffer, the type of boundary scan desired and the desired test format. Further, each of the I/O buffers that are included in the boundary scan path typically must be serially connected into a serial scan chain. Finally, a number of control signals must typically be provided to each I/O buffer in the boundary scan path.
In some designs, it may be desirable to support more than one test format. For example, some designs may support both the Test Access Port (TAP) format and the Level Sensitive Scan Design (LSSD). To implement the TAP and LSSD format boundary scan, the I/O buffers are typically required to be connected to both the TAP and LSSD scan logic, and may require unique control signals and interconnect requirements for each format. Supporting both TAP and LSSD often places a great burden on the circuit designer to manage the necessary control and test logic associated with either or both of the TAP and LSSD boundary scan formats.
Another factor which often complicates the I/O design of an integrated circuit is that the I/O pads may function differently depending on whether the integrated circuit is in a test mode or a functional mode. This may be desirable when the integrated circuit is pin limited. For example, selected output pins may be designated as inputs when in test mode, and outputs when in functional mode.
Finally, the design of the I/O section of an integrated circuit design may be complicated by the variety of I/O buffer attributes that may be required. As indicated above, some I/O pads on the die may drive higher resistance and/or capacitance than other pads. Further, some I/O buffers may be in critical timing paths, while other may not. Thus, in this example, the drive strength of each I/O buffer on the die may have to be selected to optimized the speed/power product of the overall design.
As can readily be seen, managing the I/O design, testability, and boundary scan requirements on a modern integrated circuit can be a difficult, time consuming and error prone endeavor. In addition, it is known that design changes are often required during the design process, which may result in input and output signals being reassigned to different pins, attributes of particular I/O buffers being changed, and/or the testability requirements of particular I/O buffers being change. These design changes may necessitate reconnecting large portions of the input, output, and bi-directional buffer interface logic and boundary scan logic, which may add to the difficult in managing the I/O design.
The present invention overcomes the many of the disadvantages found in the prior art by providing a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for receiving a number of parameters provided by the circuit designer. The parameters preferably provide specific information about a circuit design. A set of circuit design assembly rules are also provided, which define the available I/O cells, the available boundary scan logic modules, and the appropriate interconnections for various combinations thereof. A computer program then selects and assembles the I/O cells and boundary scan logic modules in accordance with the user provided parameters and the set of circuit design assembly rules.
In a preferred embodiment, the cells are input, output, and/or bidirectional buffers, and the boundary scan logic modules can be selected to support various test configurations. The present invention then automatically selects and interconnects selected ones of the I/O cells and boundary scan logic modules to form a number of interface modules. The I/O cells and the boundary scan blocks are selected according to the user provided parameters, and are interconnected according to the set of circuit design assembly rules. Further, the present invention may provide an appropriately configured test control block for providing the required test control signals to the interface modules. The resulting interface modules are then expressed as either a number of instantiated components or as a detailed description in a hardware description language.
Finally, the present invention contemplates providing appropriately names terminals on the interface blocks such that the interface blocks can be automatically connected to the I/O pads and core logic within a corresponding ASIC design.
The user provided parameters preferably identify a particular I/O macro cells and a particular boundary scan logic module for each of the I/O pads on the integrated circuit die. This allows the proper selection of components when assembling the interface blocks. In addition, the user provided parameters preferably include a number of fixed parameters including a pin location, a signal use, a pin capacitance, a pin resistance and a scan order. These parameters are labeled as xe2x80x9cfixedxe2x80x9d parameters because they are primarily dictated by the package design that is selected for the integrated circuit. It is also contemplated that the user provided parameters may also include a number of user specified logic circuit parameters which are related to the particular circuit at hand. Preferably, the user specified logic circuit parameters may include an ASIC terminal name, an input core signal net name, an output core signal net name, an I/O cell name, a boundary scan logic module name, an associated net, an optional spreadsheet sort field, and a test flag.
The user preferably provides the user provided parameters via a spreadsheet interface. The functions commonly provided in spreadsheet programs may be used to automatically generate or manipulate the parameters provided in the spreadsheet. For example, and in a preferred embodiment, the ASIC terminal name is automatically generated by adding a xe2x80x9cTxe2x80x9d as a suffix to the core signal net name provided in an adjacent column of the spreadsheet. Thus, the spreadsheet interface provides an efficient way to specify, evaluate and document the user specified parameters for a particular circuit design.